DFT Engineer:

1-10 year experience with Skill set : Scan insertion with Test Compression, ATPG for stuck-at and Transition faults, MBIST insertion, Memory Repair implementation and Pattern Validation, IJTAG, Boundary Scan

Design and Verification Engineer:

1-5 year experience with Skill set: Logic Desgin, RTL coding, Synthesis, Timing Check, System Verilog, UVM and scripting language.

Physical Design Engineer:

1-5 year experience with Skill set: Hierarchical Floorplanning or top-down or full chip floorplan (including IO) , partition, Time budgeting, Power planning, Placement & Optimization (Macro placement, IO placement, Synchronizer, level shifters, isolation cells) etc, CTS (Latency/local & Global Skew/Useful skew/Clock power/Boundary skew/Area/Multi-mode multi-corner aware/respecting transition times) etc, Routing, Post-Route Optimization (xtalk/SI etc), Full chip assembly from P&R abstracts