Ramic provide 16 weeks DFT training program as per current industry requirements with hands on projects as below...

Week1: VLSI Basics
- ASIC design Flow
- Verilog programming
- Synthesize
- Linux and scripting
Week2: DFT Basics
- Importance of Testing
- Fault Models
- DFT architecture at core level
- DFT architecture at SOC level
- Exposure on each DFT logic

Week3: Full Scan Insertion with Lab sessions
- Scan cell Designs
- Scan Architectures
- Scan DRC and Fix
- Scan Design Flow
- Scan insertion 

Week4: Test Compression (EDT) with Lab sessions
- Test compression techniques
- Various Test compression structures
- How to decide test compression ratio
- EDT insertion, DRC and Fix
- Masking logic

Week5: Advanced scan insertion Techniques with Lab sessions
- Shadow logic insertion
- Wrapper cells insertion
- Test-point insertion
- IEEE P1500 insertion
- On-Chip-Clock (OCC/OPCG) logic insertion  

Week6: Test Generation (ATPG) with Lab sessions
- Create Test structure and verify
- ATPG violations and Fix
- ATPG for scan chain integrity check
- ATPG for for Stuck-At faults
- ATPG for for Transition faults

Week7: ATPG Coverage Analysis with Labs sessions
- Fault coverage and Test coverage analysis
- How to analysis coverage loss
- Coverage improvement techniques
- Various experiments to improve coverage loss

Week8: Simulation with Lab sessions
- Basics of simulation
- Understanding inputs of simulation
- Chain pattern simulation
- Stuck-at and Transition patterns simulation
- Simulation issues

Week9: Simulation Debug with Lab sessions
- Debug techniques
- Scan chain patterns failure debug
- Stuck-at patterns failure debug
- Transition patterns failure debug

Week10: JTAG and IJTAG with Lab sessions
- TAP architecture
- TAP FSM behavior analysis in real time 
- IR and DR verification test
- P1500 wrapper verification- IJTAG (IEEE 1687) network- ICL and PDL

Week11: Memory Testing with MBIST
- Need of memory testing
- Memory fault models
- MBIST architecture- How to decide number of controllers for a design
- Memory test algorithms
- Memory failure debug

Week12: Memory Repair with  BIRA and BISR
- Need of memory Repair
- Redundancy memory architecture
- Repair logic architecture
- Repair implement flow

Week13: Boundary Scan (BSCAN) Testing
- Various Boundary scan cells and structure
- BSCAN network architecture
- Various tests of BSCAN
- BSCAN Description Language (BSDL)

Week14: Logic BIST (LBIST)
- Basic concepts of LBIST
- LBIST design rules and Fix
- LBIST architectures
- Pattern generation Techniques
- Output response analysis Techniques

Week15 and Week 16: Preparation for Interviews
- Revision of DFT flows
- Discuss DFT interview FAQ's
- Discuss real time issues and debug techniques
- Understand knowledge level and improvement