Design-for-testability Bangalore

DFT (Design-for-testability)

01.

Scan Insertion

02.

Test Compression

03.

MBIST and Memory Repair Implementation

04.

ATPG and Pattern Validation

05.

JTAG and Boundary Scan Implementation

RTL Design & Verification

01.

Verilog/ VHDL design

02.

Functional Verification

03.

STA

RTL Design & Verification Bangalore
Physical Design Bangalore

Physical Design

01.

Place & Route

02.

Clock Tree Synthesize

03.

Layout Design

RTL Design & Verification Bangalore